To complete EVG’s lithography and bonding portfolio, sufficient metrology is necessary to ensure process control and (in combination with feedback loops) also allow for process parameter optimization like bond alignment. Versatile measurement options are available to meet the metrology requirements for a wide variety of applications. These tools can fit in HVM and R&D environments.
Metrology is essential to control, optimize and ensure the highest yield in semiconductor manufacturing processes. Advanced packaging, MEMS and photonic applications are gaining importance, very often lacking suitable metrology solutions for essential processing steps. Furthermore, overall performance of the device is determined by packaging and back-end-of-line processes; hence, process requirements are getting tighter and need further metrology. EVG’s metrology solutions for wafer inspection and evaluation are optimized for lithography and all types of bonding applications. As one example, metrology prior to non-reworkable processes like wafer thinning after temporary bonding directly leads to increased yield and process security, where an integrated feedback loop results in a reduction of high-cost wafer scrap.
Visit our Booth S9 & listen to our talks "High–Resolution Patterning by Maskless Exposure Technology contributing to Traceability Efforts in Semiconductors" held by Dr. Varga Ksenija and "Wafer-to-Wafer and Die-to-Wafer Hybrid Bonding for Advanced Interconnects" held by Dr. Dragoi Viorel.
Visit our booth #16 & Listen to our talk "Wafer Bonding as Next Generation Scaling Booster" held by our Executive Technology Director Lindner Paul on 12 Dec, 2:15 PM as well as the AMAT IEDM Logic Panel on 12 Dec, 06:20 PM at Hotel Nikko!
12月15日 (水) - 17日 (金) 10:00-17:00
東京ビッグサイト