To complete EVG’s lithography and bonding portfolio, sufficient metrology is necessary to ensure process control and (in combination with feedback loops) also allow for process parameter optimization like bond alignment. Versatile measurement options are available to meet the metrology requirements for a wide variety of applications. These tools can fit in HVM and R&D environments.
Metrology is essential to control, optimize and ensure the highest yield in semiconductor manufacturing processes. Advanced packaging, MEMS and photonic applications are gaining importance, very often lacking suitable metrology solutions for essential processing steps. Furthermore, overall performance of the device is determined by packaging and back-end-of-line processes; hence, process requirements are getting tighter and need further metrology. EVG’s metrology solutions for wafer inspection and evaluation are optimized for lithography and all types of bonding applications. As one example, metrology prior to non-reworkable processes like wafer thinning after temporary bonding directly leads to increased yield and process security, where an integrated feedback loop results in a reduction of high-cost wafer scrap.
Besuchen Sie unseren Stand auf dem MicroNanoFabrication Annual Review Meeting 2025!
Besuchen Sie unseren Stand #L1300!
Besuchen Sie unseren Stand #330 und unser PDC „Wafer-to-Wafer and Die-to-Wafer Hybrid Bonding for Advanced Interconnects“ von Dr. Viorel Dragoi am 27. Mai und hören Sie sich auch unsere Vorträge „Advanced FO PLP Digital Lithography Patterning Development for AI Devices“ & „Wafer-to-Wafer Bonding With Saddle-Shaped Wafers“ von Dr. Ksenija Varga und Anton Alexeev am 29. Mai an. Wir freuen uns auch darauf, Sie bei der Poster Session am 29. Mai zu treffen, wo Urban Peter „IR Laser Debonding for Silicon Based Temporary Carrier Systems Enabling 2.5D and 3D Chiplet Integration Processes“ präsentieren wird.
Kontaktieren Sie die EVG-Experten