Spin coating technology is a universal and intensively used process for applying uniform thin films when no topography on the wafer is considered.
Dosing accuracy of dispensed material and spin speed are some of the most important factors in spin coating processes. Other critical process parameters such as acceleration, precise positioning or possibility to perform a dynamic dispense rate also play a significant role in coat properties. EVG spin coaters are designed to control all of these critical parameters to ensure precise resist dispensing process control. Up to eight dispense lines without temperature control or up to four temperature-controlled dispense lines enhance process set-up supporting three different dispense modes to guarantee optimum results for an extensive range of resists with viscosities up to 52.000 cP. Static or dynamic center dispense mode is recommended for typical thin-film applications and standard viscosity. Area dispense mode optimizes uniformity and resist consumption by enabling extremely uniform thick resist layers for the use of high-viscosity resists like BCB or SU-8. Moreover, edge dispense mode is a typical application for etch protection purposes, especially for long-term etch processes. For this purpose, EVG systems are equipped with programmable swivel arms supporting various flat/notch designs. Additional functions – such as solvent-based pre-wetting, edge-bead removal and automatically solvent refillable sealed park position – support advanced process control and production requirements. The programmable suck-back function prevents surplus resist from dropping out of the nozzle tip on the wafer surface and thus secures conformal results throughout the whole wafer. Optional CoverSpin reduces the amount of resist material per wafer and avoids edge turbulence effects independent of the substrate shape. Overall, EVG’s spin coat module with a simulation-based low-turbulence design effectively supports resist-saving processes while providing high-uniformity results on planar or low-topography surfaces.
Besuchen Sie unseren Stand #330 und unser PDC „Wafer-to-Wafer and Die-to-Wafer Hybrid Bonding for Advanced Interconnects“ von Process Technology Manager Tobias Wernicke am 27. Mai und hören Sie sich auch unsere Vorträge „Advanced FO PLP Digital Lithography Patterning Development for AI Devices“ & „Wafer-to-Wafer Bonding With Saddle-Shaped Wafers“ von Business Development Manager Dr. Ksenija Varga und Anton Alexeev am 29. Mai an. Wir freuen uns auch darauf, Sie bei der Poster Session am 29. Mai zu treffen, wo Supervisor Process Technology Peter Urban „IR Laser Debonding for Silicon Based Temporary Carrier Systems Enabling 2.5D and 3D Chiplet Integration Processes“ präsentieren wird.
Lauschen Sie unserer Keynote "The role of wafer bonding in next generation interconnect scaling" gehalten von Corporate Technology Development & IP Director Markus Wimplinger
Hören Sie sich unsere Vorträge am Mittwoch 18. Juni in Session 15 an:
„Investigation of influence of structure geometry on resist coverage for spray coating“ von Johanna Rimböck, Technology Development und
„Utilizing Inkjet Coating and Nanoimprinting for Complex 3D Patterns with Gradual Height Increase and Minimal Residual Layer“, gehalten von Business Development Manager Thomas Achleitner.
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