Hybrid and Fusion Bonding
Hybrid and Fusion Bonding for Engineered Substrates and 3D Device Integration
Introduction
Hybrid bonding extends fusion bonding with embedded metal pads in the bond interface, allowing for face-to-face connection of wafers. The main application for hybrid bonding is in advanced 3D device stacking.
Fusion or direct wafer bonding enables permanent connection via dielectric layers on each wafer surface used for engineered substrate or layer transfer such as backside illuminated CMOS image sensors.
Fusion or direct wafer bonding allows dielectric layers and more precisely activated dangling of functional groups to bridge between wafers with the help of hydrogen bridge bonds. This pre-bonding step takes place at room temperature and atmospheric condition. Only during a subsequent annealing step are low-energy hydrogen bridge bonds turned into covalent bonds. Fusion bonding is traditionally applied for engineered substrates and more recently to stack wafers using full-area dielectrics. Due to pre-bonding at ambient conditions, a very high alignment of less than 100 nm allows for 3D integration scenarios using wafer-to-wafer fusion bonding. In addition, copper pads can be processed in parallel with the dielectric layer, allowing one to pre-bond the dielectric layer at ambient temperature, while electrical contacting can be achieved during annealing via metal diffusion bonding. This special case is called hybrid bonding. The main applications for hybrid bonding include CMOS image sensors, memory as well as 3D system-on-chip (SoC).
Features
- Layer transfer for engineered substrates such as Silicon on insulator, RF compatible substrates, and backside illuminated image sensors
- Wafer-to-wafer interconnection with high alignment needs down to 50 nm for 3D system-on-chip devices, chip stacking and die partitioning
- Hybrid bond capability for simultaneous mechanical and electrical connection with very low connection pitch of less than 1 micron
Related products
Events
SEMICON EUROPA 2026
Treffen Sie das EVG-Team am Stand #B1241 und besuchen Sie unsere Poster-Präsentationen auf der APC:
"Software-Driven Strategies for Advanced Multi-Die Patterning in Digital Lithography" von Business Development Manager Dr. Ksenija Varga und “Leveraging Advanced Bonding Technologies to Enable Scalable Co-Packaged Optics Architectures” von Business Development Manager Elisabeth Brandl.
Hier finden Sie nähere Infos zum Program.
Darüber hinaus wird unser Corporate Sales & Marketing Director Thomas Uhrmann Teil der Podiumsdiskussion „SEMICONDUCTOR TOUR 2026“ sein, welche von der YOLE Group am 12. November im Novotel München Messe veranstaltet wird. Für mehr Informationen klicken Sie hier.
Industrial Print Integration Conference (IPI) 2026
Hören Sie sich unsere Keynote an: “Advancing AR/VR and CPO: EV Group’s Inkjet Solutions for Next-Generation Optics” gehalten vonJohanna Rimböck (Technology Development).
Mehr Informationen zum Programm finden Sie hier.
EPTC 2026
Besuchen Sie unseren Stand #2 & hören Sie sich unsere Vorträge an:
"Scalable Manufacturing Approaches for Co-Packaged Optics via NIL and Advanced Wafer Bonding" gehalten von Director Business Development Dr. Bernd Dielacher und
“Advancing 310×310 mm² Panel Level Packaging: High Throughput Pathways to High Yield 3D Integration” und “Plasma–Enabled Die Singulation on Film Frame Carrier for Advanced HBM and Logic Die Integration” von Business Development Manager Dr. Ksenija Varga.
“Hybrid Bonding Overlay Reduction Through Lithographic Pre-Compensation of the Residual Fingerprint” von Technical Program Manager Sander Grosemans.
EVG & Brewer Science: “Polymer Buffer Layer Enabling a Novel RDL–First Process Flow using a Silicon Carrier and IR Laser Debonding Technology” shared presentation, Peter Urban & Brewer Science.
EVG & CEA–Leti: “Nanometer Level Chip- Scale Transfer Enabled by IR Laser Debond Technology”.
Mehr Infos zum Programm hier.
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