IQ Aligner® NT Automated Mask Alignment System

Optimized for contactless proximity processing at highest throughput. Most accurate print gap control and unmatched uptime are fully addressing HVM requirements.

EVG IQ Aligner NT


Brochures / Flyers
Please click the picture to download the brochure in PDF format

EVG IQ Aligner NT V17-01-thumb
EVG IQ Aligner NT Flyer.pdf

EVG Mask Aligner Short Brochure.pdf

Technical Papers
Please click the titles to download the full papers in PDF format

Advances in processing of compound semiconductor substrates
Abstract: Compound semiconductor materials such as GaAs and InP have distinct advantages over the more traditional silicon, chief of which is the greater electron mobility within the substrate, allowing greater use in low-noise, high gain applications. However, the advantages of these materials come with corresponding disadvantages...

An ultra-thick positive photoresist for advanced electroplating applications
Abstract: Flip chip packaging has been adopted for microprocessors and high-performance logic for performance reasons. Over time, flip chip is increasingly being adopted by lower transistor count devices for cost savings as flip chip packaging reaches cost parity with wire bonding in many applications...

Lithography technologies for wafer-level packaging
Abstract: The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. With respect to the continuous reduction in IC feature size and with increased demand for better performance attended with the simultaneous increase of I/O, wafer-level packaging (WLP) and fine-pitch wafer bumping have become a very interesting solution for IC packaging...

Trends in aligned wafer bonding for MEMS and IC wafer-level packaging and 3D interconnect technologies
Abstract: The continuous reduction of IC feature size, the increased demand for higher speed, the lower power consumption and the simultaneous increase of I/O leads to wafer-level packaging through aligned wafer bonding as an interesting solution for IC and MEMS packaging. Portable consumer products such as wireless handsets and upcoming high-performance computing devices drive the semiconductor industry to develop advanced packaging solutions with reduced thickness and area dimensions...

Ultra-thick lithography for advanced packaging and MEMS
Abstract: An ever increasing need exists for thick resist layers in the processing of MEMS and for advanced packaging.  Applications in the MEMS field include bulk micromachining, surface micromachining, and the actual creating of active device structures... 

Wafer level packaging on Cu/low-K, high density back-end integrated circuits
Abstract: The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. Wafer level packaging is a promising technology to meet future demands of increase performance for advanced integrated circuits with tighter pitch (higher feature density) higher I/O counts and Cu metallization with low-k dielectric layers...