HERCULES® Lithography Track System

For fully automated and integrated coating, mask alignment, exposure and/or developing.


Please click the picture to download the brochure in PDF format

EVG100 Series Short Brochure.pdf

Press Releases
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February 17, 2016:
WIKA Group Adopts HERCULES® Lithography Track System From EV GROUP for Pressure Sensor Manufacturing
Demand for EVG lithography solutions continues to grow  for both mainstream and specialized applications requiring highly customizable solutions 

Technical Papers
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An ultra-thick positive photoresist for advanced electroplating applications
Abstract: Flip chip packaging has been adopted for microprocessors and high-performance logic for performance reasons. Over time, flip chip is increasingly being adopted by lower transistor count devices for cost savings as flip chip packaging reaches cost parity with wire bonding in many applications...

Lithography technologies for wafer-level packaging
Abstract: The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. With respect to the continuous reduction in IC feature size and with increased demand for better performance attended with the simultaneous increase of I/O, wafer-level packaging (WLP) and fine-pitch wafer bumping have become a very interesting solution for IC packaging...

Ultra-thick lithography for advanced packaging and MEMS
Abstract: An ever increasing need exists for thick resist layers in the processing of MEMS and for advanced packaging.  Applications in the MEMS field include bulk micromachining, surface micromachining, and the actual creating of active device structures... 

Wafer level packaging on Cu/low-K, high density back-end integrated circuits
Abstract: The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. Wafer level packaging is a promising technology to meet future demands of increase performance for advanced integrated circuits with tighter pitch (higher feature density) higher I/O counts and Cu metallization with low-k dielectric layers...