Wafer level packaging employs specific alignment and wafer bonding
techniques as an enabling solution for stacking of wafers and
three-dimensional integration of devices.
Visit us at our booth #208 at ECTC 2016.
Visit us at our booth #1017 at SEMICON West 2016.
Visit us at ICEPT 2016.
Visit our booth # 7 at ESTC 2016.
Visit us at our booth #950 at SEMICON EUROPA 2016.
JOANNEUM RESEARCH and EV Group Jointly Develop Large-Area Nanoimprint Lithography Solution
EV Group and Fraunhofer IZM-ASSID Establish JDA for High-Volume 3D Integration Applications
EV Group Corporate Video