Wafer level packaging employs specific alignment and wafer bonding
techniques as an enabling solution for stacking of wafers and
three-dimensional integration of devices.
Meet us at the 13th Annual Conference 3D Architectures for Semiconductor Integration and Packaging (3D ASIP).
Join EVG at SEMICON Japan 2016 in Tokyo, JapanEVG Booth: Hall 5 #5528Exhibitors Seminar: EVG Solutions for "Mid-end" TechnologiesDecember 15, 2016, 15:00 - 15:50, Exhibitors Seminar Room (Hall 4)
AngeLab project receives Innovation Award at the European Nanoelectronics Forum
30.2 Percent Efficiency - New Record for Silicon-Based Multi-Junction Solar Cell
3D ASIP 2016
SEMICON Japan 2016
EV Group and Fraunhofer IZM-ASSID Establish JDA for High-Volume 3D Integration Applications
EV Group Corporate Video