先进封装,三维层叠互联

Wafer level packaging employs specific alignment and wafer bonding techniques as an enabling solution for stacking of wafers and three-dimensional integration of devices.


 
ectcECTC 2016
May 31 - June 3, 2016, The Cosmopolitan of Las Vegas, NV

Visit our booth #208 and the paper presentation titled "Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors, co-authored by EVG  at ECTC 2016 .


semiconwest16SEMICON West 2016
July 12 - 14, 2016, Moscone Center, San Francisco, California

Visit us at our booth #1017 at SEMICON West 2016.


welcome_img_iceptICEPT 2016
August 16 - 19, 2016, Wuhan, China

Visit us at ICEPT 2016.


ESTC_finalESTC 2016
September 13 - 15, 2016, Grenoble, France

Visit our booth # 7 at ESTC 2016.


semiconmicro_logoSEMICON EUROPA 2016
October 25 - 27, 2016, Grenoble, France

Visit us at our booth #950 at SEMICON EUROPA 2016.