先进封装,三维层叠互联

Wafer level packaging employs specific alignment and wafer bonding techniques as an enabling solution for stacking of wafers and three-dimensional integration of devices.


 
3DASIPheader1200new_20163D ASIP 2016
December 13 - 15, 2016, San Francisco, CA, USA

SCJapan_RGB_msSEMICON Japan 2016
December 14 - 16, 2016, Tokyo, Japan

Join EVG at SEMICON Japan 2016 in Tokyo, Japan
EVG Booth: Hall 5 #5528
Exhibitors Seminar: EVG Solutions for "Mid-end" Technologies
December 15, 2016, 15:00 - 15:50, Exhibitors Seminar Room (Hall 4)