Chip Stacking for 3D IC

One of the key drivers behind 3D integration is the reduced design and manufacturing complexity compared to a system-on-chip (SoC) approach, for example. Individual functional entities of a device can be manufactured on different wafers, in different fabs and even by different companies. This concept enables a modular approach, whereby application-specific components can be integrated with standardized components. There are 3 fundamentally different vertical integration schemes: chip-to-chip (C2C), chip-to-wafer (C2W) and wafer-to-wafer (W2W) integration. C2W integration enables higher flexibility then W2W. First and foremost, with C2W the dies can vary in size, whereas for W2W integration, the dies must be the same size. Compound semiconductor wafers with 300 mm diameter are typically not available. Heterogeneous integration for RF, optical or high frequency applications thus requires a C2W integration scheme.

The required alignment accuracy is an important decision criterion. The International Technology Roadmap for Semiconductors (ITRS) for high density through silicon via (TSV) applications [1] defines bonding overlay accuracy of 1.0 ìm (3 sigma) for 2010-2012 and 0.5 ìm (3 sigma) starting in 2013. The ITRS alignment accuracies are being met by modern W2W alignment systems (see dedicated section on the site). The W2W alignment process is sufficiently fast to support multiple wafer bonding chambers. However, for C2W alignment there is a trade-off between alignment accuracy and throughput. Sub-micron alignment accuracy is achievable on systems with very low throughput of only a couple of hundred dies per hour. For high volume production systems with a throughput of up to 10,000 dies per hour, the achievable alignment accuracy is limited due to the inherent problem of self-induced vibrations. Typical alignment specifications for C2W integration in high volume manufacturing are in the range of 3-10 ìm (3 sigma).

Yield is one of the most important considerations for any 3D integration scheme. C2W enables known good die (KGD) manufacturing as both the wafer and the singulated dies can be tested prior to stacking. There are several open technical and logistical questions, but technically C2W integration allows true KGD manufacturing. For W2W integration, this is not possible. Even though wafers can be tested prior to bonding and bond partners can be matched, there is always the risk that a good die on the first wafer gets bonded to a bad die on the second wafer.

Throughput for W2W bonding is independent of the die size, as all dies are processed in parallel. C2W bonding, on the other hand, requires serial chip placement, which means that the process time per wafer is highly dependent on the die size. (Figure 1)

Wafer bonding is a fab-compatible process, and a bonded wafer stack can be processed on standard wafer processing equipment. C2W integration does not offer the same level of cleanliness. Standard cleaning procedures for wafers (and bonded wafers) cannot be applied to wafers populated with isolated dies.

The desired thickness of the stackable dies is an important question. Temporary bonding to a carrier wafer enables handling and processing of ultra-thin wafers. For W2W integration, these thin wafers can be bonded to another device wafer prior to debonding. In that, case the carrier wafers are reusable. For C2W integration, dies with a thickness of less than 25 ìm have to be singulated together with the carrier wafer prior to stacking and debonding of the carrier die [2]. The carrier wafer cannot be reused, which adds to the cost per wafer.

3D stacking with TSV-chips requires electrical contacts within the bond interface. It is possible to create the TSVs prior to the bonding or after bonding. One of the advantages of creating the TSVs prior to bonding is that the mechanical bond, as well as the electrical connection, can be established simultaneously during the bond process. Due to reliability reasons, it is not possible to use traditional solder reflow schemes for small via diameter or small pitch. Instead, it is necessary to apply metal bonding schemes like transient-liquid phase (TLP) bonding, e.g., copper-tin (Cu-Sn), or thermo-compression bonding, e.g., Cu-Cu. These processes are based on metal ion diffusion. The reaction kinetics for these diffusion processes is proportional to temperature, pressure and time. To achieve reasonable process times for production purposes, it is necessary to perform the bond process at elevated temperatures of 200-400°C while applying high pressure onto the bond interface. Even under these optimized conditions, the bond process takes between 5 and 30 minutes. It would not be economically feasible to perform C2W bonding serially, as it would take many hours or even days to process one wafer.

[1] ITRS 2008 Update,
[2] RTI 3D conference 2008, talk Bart Swinnen, IMEC

Figure 1: Throughput comparison: W2W alignment versus C2W pick-and-place