Wafer Bonding for 3D IC

There are three main wafer bonding methods for 3D interconnects: fusion (or molecular) bonding, adhesion thermo-compression bonding and metal-metal thermo-compression bonding. In addition, there are hybrid methods, such as simultaneous adhesive-metal bonding or simultaneous fusion-metal bonding. Each of these methods offers advantages.

Fusion wafer bonding
Fusion wafer bonding brings several advantages:

  • Highest alignment accuracy: Fusion wafer bonding is a 2-step process consisting of a room temperature bonding step and an annealing step at elevated temperature. The room temperature bonding completely eliminates misalignment based on thermal expansion of the wafers. Sub-micron post bond alignment accuracy is routinely achieved on the GEMINI FB wafer bonding system with SmartView NT alignment.
  • Highest throughput: Fusion wafer bonding has the highest throughput compared to adhesive or metal-metal thermo-compression bonding, as it is a room temperature process. It can be implemented either in-situ in the aligner module or ex-situ under vacuum in a bond module. The subsequent annealing can be performed as a batch process in a furnace or oven.
  • Inspection capability after pre-bonding prior to final annealing: After the room temperature pre-bonding step, the bond strength is sufficiently high to enable inspection of bond quality and alignment accuracy. In case of misalignment or bond quality problems, e.g., voids, the wafer pair can be separated and reworked. This concept of inspection and, if necessary, reworking prior to final annealing has been used in SOI wafer manufacturing for many years.
  • Low cost-of-ownership: The combination of in-situ bonding in the aligner module, high throughput, increased yield due to the ability to rework, and reduced capital costs results in low cost-of-ownership for manufacturing schemes based on fusion wafer bonding.

Fusion wafer bonding is a 2-step process consisting of room temperature pre-bonding and annealing at elevated temperature. The classic annealing schemes, which were developed for SOI wafer manufacturing, require annealing temperatures in the range of 800-1100°C. A novel surface pre-processing step, LowTemp™ plasma activation, enables the wafer surface to be modified so that the annealing temperatures can be reduced to 200-400°C. LowTemp™ plasma activation enables fusion wafer bonding to be used for 3D integration.

Cu-Cu wafer bonding
Copper (Cu) is a well-understood material in modern CMOS manufacturing lines. As the metal layers of high performance chips are already made of Cu, using the top Cu layer for wafer bonding is a logical next step. Moreover, Cu-Cu bonding is favored by the industry for TSV integration because it simultaneously forms both mechanical and electrical connections. This allows integration schemes like "via-middle," in which the TSVs are processed prior to stacking. Cu-Cu thermo-compression bonding is the most prominent metal-metal bonding method for 3D interconnects. The main mechanisms for metal-metal thermo-compression bonding are metal ion diffusion and diffusional creep. The diffusion rate depends on the temperature, the pressure and the time. The maximal bonding temperature is limited by thermal budget of the devices. In addition, a higher bonding temperature increases the cycle time due to the longer heating and cooling ramps. Today's wafer bonder can apply up to 100kN force.
Adhesive wafer bonding
There are 2 main advantages to using an adhesive wafer bonding method. First, the surface roughness requirements are significantly lower. In comparison to metal thermo-compression bonding, a rough surface does not reduce the contact area for intermediate layer bonding, as there is no direct contact between the two wafer surfaces. In addition, most adhesives are reflowing during heat up. Particles on the wafer surface are embedded in the adhesive. Therefore, this bonding method is not sensitive to particles at all.