EVG®620 Automated Mask Alignment System

Mask Alignment System designed for optical double-side lithography. Volume production types and manual R&D systems are available.

 

Brochures
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EVG Mask Aligner Short Brochure.pdf

Technical Papers
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Adhesive wafer bonding with photosensitive polymers for MEMS fabrication
Abstract: Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young’s modulus, and good adhesion to different substrates.
 

Adhesive Wafer Bonding With SU-8 Intermediate Layers For Micro-Fluidic Applications
Abstract: Recently adhesive wafer bonding using SU-8 has gained a lot of interest for micro-fluidic devices e.g. lab-on-chip applications. Due to its specific properties as well as the capability to pattern thin and thick layers accurately, SU-8 is an ideal candidate for micro-fluidic components like channels, reservoirs and valves, but also for micro-optical components...



Advances in processing of compound semiconductor substrates
Abstract: Compound semiconductor materials such as GaAs and InP have distinct advantages over the more traditional silicon, chief of which is the greater electron mobility within the substrate, allowing greater use in low-noise, high gain applications. However, the advantages of these materials come with corresponding disadvantages...



An ultra-thick positive photoresist for advanced electroplating applications
Abstract: Flip chip packaging has been adopted for microprocessors and high-performance logic for performance reasons. Over time, flip chip is increasingly being adopted by lower transistor count devices for cost savings as flip chip packaging reaches cost parity with wire bonding in many applications...



Lithography technologies for wafer-level packaging
Abstract: The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. With respect to the continuous reduction in IC feature size and with increased demand for better performance attended with the simultaneous increase of I/O, wafer-level packaging (WLP) and fine-pitch wafer bumping have become a very interesting solution for IC packaging...



Ultra-thick lithography for advanced packaging and MEMS
Abstract: An ever increasing need exists for thick resist layers in the processing of MEMS and for advanced packaging.  Applications in the MEMS field include bulk micromachining, surface micromachining, and the actual creating of active device structures... 



Wafer level packaging on Cu/low-K, high density back-end integrated circuits
Abstract: The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. Wafer level packaging is a promising technology to meet future demands of increase performance for advanced integrated circuits with tighter pitch (higher feature density) higher I/O counts and Cu metallization with low-k dielectric layers...