Singapore, 15 June 2011 - The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) has launched its 11th Electronic Packaging Research Consortium (EPRC11) to address various technology challenges in advanced packaging technology in semiconductor in enabling smaller and smarter devices. Since IME initiated the first EPRC in 1996, this resource and cost-sharing platform has injected invaluable R&D capabilities into the operations of many local enterprises and multi-national companies in the electronic packaging industry and its value chain.
EPRC11 consists of 23 company members spanning the whole supply chain of the industry from system, integrated device manufacturer, foundry, assembly & test, to equipment and material companies. These include, Atotech S.E.A. Pte Ltd, Advanpack Solutions Pte Ltd, ASM Technology Singapore Pte Ltd, Disco Hi-Tec (S) Pte Ltd, Dow Corning Corporation, EV Group (EVG), GLOBALFOUNDRIES Singapore Pte Ltd, Heraeus Materials Singapore Pte Ltd, Hitachi Chemical Co., Ltd, Hisilicon Technologies Co. Ltd, Ibiden Singapore Pte Ltd, Infineon Technologies Asia Pacific Pte Ltd, OM Group Inc, Nissan Chemical Industries, Ltd, NEPES Pte Ltd, NXP Semiconductors, Optitune Pte. Ltd, Rolls-Royce Singapore Pte Ltd, Shanghai Sinyang Semiconductor Materials Co. Ltd, Sekisui Chemical Co. Ltd, Silecs International Pte Ltd, Tokyo Ohka Kogyo Co. Ltd and United Test and Assembly Center Ltd (UTAC), along with A*STAR Institute of High Performance Computing (IHPC) in four projects over the 18-month duration.
Professor Dim-Lee Kwong, IME’s Executive Director said, “EPRC started 15 years ago and we have gone through 10 cycles of projects with our members, offering high quality R&D expertise in IC packaging. The success of this consortium since 1996 is a testimony to the significance of this platform in offering companies engaged in pre-competitive R&D and looking to develop new capabilities to stay ahead of their competitors. While lending support to our local community in this frontier, IME is well-positioned on the roadmap to catalyse a suite of offerings in technological advancement and knowledge transfer to enhance the process innovations. We are confident to serve as a stepping stone in this new cycle and welcome the rigour in transforming the technological landscape. IME is committed to engage packaging solutions as we continue to see smaller and smarter products in the market.”
The four projects identified are namely Multiple Chip Embedded Wafer Level Packaging to address the re-construction process challenges and develop validated numerical models; Through Silicon Via (TSV) Interposer project to explore design, integration method, package reliability assessment, high aspect-ratio TSV and high density back-end-of-line (BEOL) wiring on multiple heterogeneous chips on a common package platform; the Fine Pitch Flip Chip with Cu Pillar project aims to develop a low-stress Cu pillar flip-chip technology on Cu low-k chips while the High Performance Materials for Advanced Packaging project focuses on high conductive packaging materials to develop new modelling methodologies and processes required for these packages.