The Advanced Chip-to-Wafer (AC2W) bonding concept separates the two processes of chip placement on the wafer and the actual chip-to-wafer bonding process. The individual chips are temporarily bonded to the processed wafer using a volatile adhesive. The partially or fully populated wafer is then transferred to a bond chamber, where the permanent bond is established by applying force and temperature in an inert or reducing environment. (Figure 1)
The closed chamber design enables an inert environment that avoids oxidation of the bond pads. In addition, a reducing atmosphere can be created by forming gas or formic acid enriched nitrogen, which allows removal of surface oxides.
The post-bond alignment accuracy of C2W integration depends on the alignment capability of the pick-and-place system, the pre-bond alignment accuracy, the capability of the bonding system to maintain the alignment accuracy during the bond process, and the process parameters. The chip thickness variation has a significant impact on the post-bond alignment accuracy. Typically, the individual chips will originate from different wafers, which might have different thicknesses due to wafer thinning inaccuracies. This chip thickness variation has to be compensated for by using a compliant layer on the bonding equipment. The compliancy capability has been qualified for 3 ìm thickness variation for 1 mm lateral distance .
Maintaining the alignment accuracy requires that pressure during bonding be only applied perpendicular to the bond interface of each die. Due to throughput optimization, it is highly advantageous not to place dies on known bad dies on the base wafer. Avoiding this action results in partially populated base wafers, which require an adjustable force application of the bonding system to ensure that the force is applied on each die in a purely perpendicular fashion. Figure 2 shows the concept of adjustable force application.
 A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen, E. Beyne, Simultaneous Cu-Cu and compliant dielectric bonding for 3D stacking of ICs, IITC, June 4-6, 2007, Burlingame
Figure 1: Process flow for the Advanced Chip-to-Wafer (AC2W) bonding concept; The individual chips are temporarily bonded to the processed wafer using a volatile adhesive. The partially or fully populated wafer is then transferred to a bond chamber, where the permanent bond is established by applying force and temperature in an inert or reducing environment.
Figure 2: Adjustable force application enables true known good die (KGD) manufacturing.