Advanced packaging techniques such as wafer bumping, 3D Interconnect,
and chip scale packaging allow different components of an integrated
circuit (IC) to be stacked on each other and directly connected, rather
than side by side on a printed circuit board. These new packaging methods
enable the production of ICs with reduced cost, lower power consumption and
higher performance.
Wafer bumping or three-dimensional stacking of wafers for wafer level
packaging employs specific alignment and lithography. EVG's mask aligners
offer full field proximity exposure and dark field alignment up to 300 mm.
Wafer-to-wafer bond aligners support micron level face-to-face alignment
for 3D interconnects.
Wafer level packaging techniques use wafer bonding as an enabling solution
for stacking of wafers and three-dimensional integration of devices.
EVG offers flexible wafer bonding systems with a unique bond chamber design
to perform different wafer bonding processes. High vacuum or high pressure
conditions can be applied to achieve a uniform and strong bond.
Suitable for small diameter substrates up to 300 mm EVG's wafer bonding
systems ensure the advancement of promising new packaging techniques.
Wafer stacking has become a viable solution to reduce actual die size for
new IC packaging applications. The SmartView Aligner offers a proprietary
method for micron level face-to-face wafer level alignment. This alignment
technique is key to achieving the required accuracy in multiple wafer
stacking for leading edge technologies. SmartView technology combined with
the Gemini wafer bonding systems allows stacking of wafers through
face-to-face alignment and subsequent permanent bonding to form electrical
or optical interconnects between wafers.