SmartView® Automated Bond Alignment System for Universal Alignment

For wafer-to-wafer alignment via alignment keys in bond interface.

 

Brochures
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EV Group Bond Aligner Brochure.pdf
 

Technical Papers
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Vertical Integration through Aligned Permanent Bonding Techniques
Abstract: Through-silicon-via (TSV) interconnects can provide the shortest length and the highest density with significantly reduced signal delay and power consumption. Due mainly to a thermal budget of CMOS devices, bonding processes compatible with CMOS processing are limited only to solder-based bonding, plasma-assisted oxide bonding, direct Cu-Cu bonding, polymer adhesive bonding, and metal-polymer hybrid bonding.



Effects of Bonding Process Parameters on the Interfacial Properties of Cu-Cu Direct Bonds for TSV Integration
Abstract: Cu-Cu direct bonding facilitates fine-pitch interconnection with low electrical resistivity and high EM resistance. However, reliable Cu-Cu bonding stems only from high temperature, high pressure and long process time mainly because of its tendency to generate a native oxide which deadly impacts device reliability.



3D interconnect through aligned wafer level bonding
Abstract: Wafer Level Packaging and 3-D Interconnect Technologies are driven by the increasing device density, functionality as well as the reduction of total packaging costs. Many devices such as PDAs, memory cards, smart cards and cellular phones utilize the resulting chip scale packages. Key enabling technologies for 3D Interconnect are high precision alignment and bonding systems and thick resist processing...



3D process integration – wafer-to-wafer and chip-to-wafer bonding
Abstract: Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes...



Aligned fusion wafer bonding for wafer-level packaging and 3D integration
Abstract: Wafer-level packaging via wafer bonding allows smaller and thinner packages, improves the yield due to higher cleanliness, enables the encapsulation of vacuum or process gas and finally reduces the packaging costs significantly. High precision alignment of device wafer to cap wafer allows real chip size packaging as the required width of the sealing rings is in the low micron range...



Aligned low temperature wafer bonding for MEMS manufacturing: challenges and promises
Abstract: The increased complexity of current generations of MEMS devices imposes new requirements for wafer bonding. Among these can be mentioned low process temperature (<400°C), precise optical alignment of substrates, ability to bond a large variety of substrates and the possibility to bond with defined intermediate layers...



Effects of bonding process parameters on wafer-to-wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding
Abstract: Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential...



New Challenges for 300 mm Si Technology - 3D Interconnects at Wafer Scale by Aligned Wafer Bonding
Abstract: A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 µm...



Plasma activated wafer bonding: the new low temperature tool for MEMS fabrication
Abstract: Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stressfree, aligned substrates without warpage...



Trends in aligned wafer bonding for MEMS and IC wafer-level packaging and 3D interconnect technologies
Abstract: The continuous reduction of IC feature size, the increased demand for higher speed, the lower power consumption and the simultaneous increase of I/O leads to wafer-level packaging through aligned wafer bonding as an interesting solution for IC and MEMS packaging. Portable consumer products such as wireless handsets and upcoming high-performance computing devices drive the semiconductor industry to develop advanced packaging solutions with reduced thickness and area dimensions...



Wafer level packaging on Cu/low-K, high density back-end integrated circuits
Abstract: The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. Wafer level packaging is a promising technology to meet future demands of increase performance for advanced integrated circuits with tighter pitch (higher feature density) higher I/O counts and Cu metallization with low-k dielectric layers...