Advanced Packaging, 3D Interconnect

Wafer level packaging employs specific alignment and wafer bonding techniques as an enabling solution for stacking of wafers and three-dimensional integration of devices.

Technical Papers
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Equipment and Process Solutions for Low Cost High Volume Manufacturing of 3D Integrated Devices
Abstract:
With end applications in the high performance server, mobile computing and smart phone space demanding ever higher performance of microelectronic devices while reducing power consumption and package size, the industry is preparing for the market introduction of 3D stacked devices based on TSV technology...
 


Wafer Bonding for Backside Illuminated Image Sensors
Abstract:
Backside illuminated image sensors combine small pixel area with high
signal-to-noise ratio. Wafer bonding is a key enabling process step for manufacturing of backside illuminated image sensors. The fully CMOS processed image sensor wafer is bonded to a blank silicon carrier wafer and then back thinned to reveal the photodiodes...



Results on Aligned SiO2 /SiO2 Direct Wafer-to-Wafer Low Temperature Bonding for 3D Integration
Abstract:
To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxideoxide direct bonding on 200mm with and without copper
level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.



Wafer Level Processing and Integration Techniques for CMOS Image Sensor Module Manufacturing
Abstract:
Image sensors have become ubiquitous, appearing in cellular phones, car sensors, notebook webcams, digital cameras, video camcorders, and security & surveillance systems. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications...



Wafer Bonding for Backside Illuminated CMOS Image Sensors Fabrication
Abstract:
Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area...



Advanced Chip-to-Wafer Bonding Enabling Silicon-in-Package (SiP) Production with Low Cost of Ownership
Abstract: The shrinkage and integration of various functionalities into electrical devices such as computers or mobile phones has lead to an ongoing need for shrinkage of the integrated semiconductor units as well. One possibility for manufacturing highly integrated electrical devices is the System-in-Package (SiP) approach where various semiconductor chips with different functionalities are stacked and electrically connected to each other...



Lithography and Wafer Bonding Solutions for 3D Integration
Abstract: The advantages as well as the technical feasibility of through silicon vias (TSV) have been acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of lithography, thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps...
 

Photolithography in Vertical Vias for 3D TSV
Abstract:
Currently there are several strategies in use for 3D TSV packaging. One of them, mostly used for CMOS image sensor packaging, requires in its process flow creation of a dielectric layer which insulates the backside via’s metal filling from the sidewalls. This insulating layer has to be opened in the bottom of the via in order to allow electrical contact between the front side of the wafer and the via filling. This contact can be created by etching through a resist mask, i.e. a conformal layer of photosensitive resist coated over the via topography with a well-defined opening on the bottom...



Wafer Bonding for 3D-Interconnect Applications
Abstract: Wafer bonding has been used for Micro-Electro-Mechanical Systems (MEMS) devices manufacturing for the last two decades. Combined with advanced packaging techniques such as wafer bumping, 3D Interconnect, and chip scale packaging wafer bonding allows different components of an integrated circuit (IC) to be stacked (vertical integration concept) and directly connected, rather than side by side in printed circuit board (PCB) technology...



Vertical Integration through Aligned Permanent Bonding Techniques
Abstract: Through-silicon-via (TSV) interconnects can provide the shortest length and the highest density with significantly reduced signal delay and power consumption. Due mainly to a thermal budget of CMOS devices, bonding processes compatible with CMOS processing are limited only to solder-based bonding, plasma-assisted oxide bonding, direct Cu-Cu bonding, polymer adhesive bonding, and metal-polymer hybrid bonding.



Effects of Bonding Process Parameters on the Interfacial Properties of Cu-Cu Direct Bonds for TSV Integration
Abstract: Cu-Cu direct bonding facilitates fine-pitch interconnection with low electrical resistivity and high EM resistance. However, reliable Cu-Cu bonding stems only from high temperature, high pressure and long process time mainly because of its tendency to generate a native oxide which deadly impacts device reliability.



Integration of a Temporary Carrier in a TSV Process Flow
Abstract: Three-dimensional (3-D) wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1-3]. To stack wafers, reliable throughsilicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling...


 
3D interconnect through aligned wafer level bonding
Abstract: Wafer Level Packaging and 3-D Interconnect Technologies are driven by the increasing device density, functionality as well as the reduction of total packaging costs. Many devices such as PDAs, memory cards, smart cards and cellular phones utilize the resulting chip scale packages. Key enabling technologies for 3D Interconnect are high precision alignment and bonding systems and thick resist processing...



3D process integration – wafer-to-wafer and chip-to-wafer bonding
Abstract: Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes...



Advanced chip-to-wafer technology: Enabling technology for volume production of 3D system integration on wafer level
Abstract: A continuous demand for electronic devices with more advanced functionality, in addition to decreased size and weight calls for ever-increasing integration and complexity. 3D system integration using chip-to-wafer technology offers the highest integration and performance of chip technology in combination with the flexibility and time-to-market advantages of packaging technology...



Aligned fusion wafer bonding for wafer-level packaging and 3D integration
Abstract: Wafer-level packaging via wafer bonding allows smaller and thinner packages, improves the yield due to higher cleanliness, enables the encapsulation of vacuum or process gas and finally reduces the packaging costs significantly. High precision alignment of device wafer to cap wafer allows real chip size packaging as the required width of the sealing rings is in the low micron range...



Aligned low temperature wafer bonding for MEMS manufacturing: challenges and promises
Abstract: The increased complexity of current generations of MEMS devices imposes new requirements for wafer bonding. Among these can be mentioned low process temperature (<400°C), precise optical alignment of substrates, ability to bond a large variety of substrates and the possibility to bond with defined intermediate layers...



An ultra-thick positive photoresist for advanced electroplating applications
Abstract: Flip chip packaging has been adopted for microprocessors and high-performance logic for performance reasons. Over time, flip chip is increasingly being adopted by lower transistor count devices for cost savings as flip chip packaging reaches cost parity with wire bonding in many applications...



Effects of bonding process parameters on wafer-to-wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding
Abstract: Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential...



Lithography technologies for wafer-level packaging
Abstract: The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. With respect to the continuous reduction in IC feature size and with increased demand for better performance attended with the simultaneous increase of I/O, wafer-level packaging (WLP) and fine-pitch wafer bumping have become a very interesting solution for IC packaging...



New Challenges for 300 mm Si Technology - 3D Interconnects at Wafer Scale by Aligned Wafer Bonding
Abstract: A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 µm...



Temperature reduced direct bonding by plasma assisted wafer surface pre-treatment
Abstract: As standard wafer bonding processes require typically a high temperature annealing step, this limits the use of wafer bonding. Due to the need to expand the applications field, low temperature (<400°C) wafer bonding processes were developed. One promising technology is plasma activated wafer bonding...



Trends in aligned wafer bonding for MEMS and IC wafer-level packaging and 3D interconnect technologies
Abstract: The continuous reduction of IC feature size, the increased demand for higher speed, the lower power consumption and the simultaneous increase of I/O leads to wafer-level packaging through aligned wafer bonding as an interesting solution for IC and MEMS packaging. Portable consumer products such as wireless handsets and upcoming high-performance computing devices drive the semiconductor industry to develop advanced packaging solutions with reduced thickness and area dimensions...



Ultra-thick lithography for advanced packaging and MEMS
Abstract: An ever increasing need exists for thick resist layers in the processing of MEMS and for advanced packaging.  Applications in the MEMS field include bulk micromachining, surface micromachining, and the actual creating of active device structures...
 


Wafer Bonding of Plasma Activated Surfaces
Abstract: Wafer bonding behavior of plasma activated Si and SiO2 surfaces was investigated. Process evaluation was performed by various experiments. Surface energy of wafer pairs bonded after different storage times at room temperature and after thermal annealing at 300°C was investigated as a measure of surface activation lifetime...



Wafer level packaging on Cu/low-K, high density back-end integrated circuits
Abstract: The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. Wafer level packaging is a promising technology to meet future demands of increase performance for advanced integrated circuits with tighter pitch (higher feature density) higher I/O counts and Cu metallization with low-k dielectric layers...



Wafer-scale BCB resist-processing technologies for high density integration and electronic packaging
Abstract: IC performance is drastically limited by line-to-line capacity coupling and RC interconnect delay times resulted from the continuous increase in integration densities with 0.10µm line and space width approaches, as well from increased signal frequencies. The new achievements in terms of circuit lines shrinkage emphasize the need for the introduction of Cu and low-k dielectric materials...