Wafer level packaging employs specific alignment and wafer bonding
techniques as an enabling solution for stacking of wafers and
three-dimensional integration of devices.
EV Group Breaks Speed and Accuracy Barrier in Mask Alignment Lithography for Semiconductor Advanced Packaging
Imec and EVG demonstrate for the first time 1.8µm pitch overlay accuracy for wafer bonding
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CMOS Image Sensors
Logic / Memory
Wafer Level Optics
EV Group and Fraunhofer IZM-ASSID Establish JDA for High-Volume 3D Integration Applications
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