Wafer level packaging employs specific alignment and wafer bonding
techniques as an enabling solution for stacking of wafers and
three-dimensional integration of devices.
Imec and EVG demonstrate for the first time 1.8µm pitch overlay accuracy for wafer bonding
EVG and NNFC announced results on improved transparent nanostructured anti-reflective coatings for next-gen displays
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SEMI European 3D Summit 2017
SEMICON Korea 2017
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CMOS Image Sensors
Logic / Memory
Wafer Level Optics
EV Group and Fraunhofer IZM-ASSID Establish JDA for High-Volume 3D Integration Applications
EV Group Corporate Video