Wafer level packaging employs specific alignment and wafer bonding
techniques as an enabling solution for stacking of wafers and
three-dimensional integration of devices.
Courtesy of Enthone.
80µm SU-8 resist features with sidewall angles approaching
Courtesy of DALSA Corporation.
High-Q-3D solenoid industors for RF ICs. Courtesy of
Sub 0.5µm aligned, bonded color filter. Courtesy of
MicroEmissive Displays (MED).
Micro-lens structures for CMOS image sensor modules created
utilizing UV-NIL. Source EVG.
Ziptronix direct bond interconnect. Courtesy of Ziptronix.
NanoSpray coating, 100µm diameter and 300µm depth. Source
Patterned, spray coated resist layer in anisotropically
etched cavity. Courtesy of TU-Delft DIMES.
Cross-section of temporary bond utilizing Brewer Science's
adhesive. Source: EVG.
200mm chip-to-wafer bond. Courtesy of Datacon.
Metal/Adhesive via first 3D bonding interface. Courtesy of
EV Group Scores Fourth Consecutive Triple Crown Win in Annual VLSIresearch Customer Satisfaction Survey
EV Group Receives Multiple Orders for GEMINI® FB XT Fusion Bonder for 3D Chip Stacking Production Applications
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SEMICON West 2016
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CMOS Image Sensors
Logic / Memory
Wafer Level Optics
EV Group and Fraunhofer IZM-ASSID Establish JDA for High-Volume 3D Integration Applications
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