Today, wafer level packaging (WLP) is a mainstream technology in micro electro mechanical systems (MEMS), advanced complementary metal oxide semiconductor (CMOS) and compound semiconductor devices. WLP helps reduce costs and ramp to high production volumes, enabling batch fabrication packaging processes, compact package sizes and increased functional density, to name a few.
The new EVG® 120 features multiple advantages for this versatile packaging market:
- Flexibility and versatility for varying process needsa
- Compact design for highest productivity at a reduced footprint
- Coating of thick and thin films for bumping, cavity definition or redistribution
- Varying pumps and dispense systems for different resist volumes and
- Highest coating uniformity via EVG's CoverSpin™
- Spray Coating for uniform coating of high topographies using EVG's
proprietary OmniSpray® coating technology
- Developing of thin and thick resistswith varying approaches, e.g. megasonic cleaninga
- Full automation for high yield and low costa
Thick-film coating technology plays a central role for all kinds of advanced packaging technologies, such as:
- Electroplated structures, such as solder bumps or redistribution layers (RDLs)
- Encapsulant films for cavity sealing rings
- Dielectric films for improved high frequency performance
- Stress buffer layers for increased reliability
EVG's resist processing technology for thick-film packaging involves the following process steps:
- Coating and patterning of sacrificial spacers, defining the cavity dimensiona and volume
- Etch mask generation for openings in inorganic films such as oxide- or nitride-based capping layers
- Direct patterning of photoactive polymer encapsulates, such as SU8, BCB or ShinEtsu SINR™
- Wet chemical sacrificial layer removal of over coating and enclosure device cavities
- Etch mask patterning or lithographic opening of electrical contacts
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EVG® proprietary OmniSpray® resist atomization nozzle
® Logo in 400µm SU-8 on 6" Wafer
The increasing consumption of MEMS in consumer applications is a key driver for improving MEMS manufacturing technologies to support novel device functionalities and application areas, reduce process time and costs, and increase yields. MEMS devices often require photolithographic processes to produce high aspect ratio structures with resist thicknesses of up to 500µm and aspect ratios of 1:25. These parameters contribute substantially to production time and cost, and have been the subject of intense R&D activities within EVG and its supplier and partner network.
As a result of these activities, a megasonic-enhanced photoresist developer module was designed and implemented for the EVG1xx resist processing equipment family.
Megasonic agitation of fluids has been originally developed for wafer cleaning processes. The acoustic waves are optimized for producing cavitation, the formation and activation of gas and vapor bubbles in fluids. The cavitation stirs the fluid and accelerates the transport of fresh solvent. The collapse of the cavities can initiate so-called sonochemical processes, resulting in an increased chemical reactivity of the solvent. In the past megasonic enhanced resist developing was mostly applied in a fluid tank as batch process.
The EVG developer module is a single-wafer spin process station equipped with a triangular-shaped megasonic area transducer. This transducer covers a sector of the wafer and is placed in proximity to the rotating substrate. A layer of process fluid is maintained underneath the transducer and the pie shape of the transducer ensures that acoustic energy density is uniformly distributed across the rotating wafer. For thick-resist processing, the application of acoustic energy improves process uniformity and efficiency in material consumption, and decreases process time. Excellent performance has been achieved for SU-8 resists [1,2].
The EVG MegPie single-wafer development module is a MEMS-qualified and cost-effective tool, and is available in the new EVG120 fully automated resist processing tool. Considerable cost savings due to optimized solvent consumption, increased yield and process time reduction from a few hours down to a few minutes have been achieved.
 V. Dragoi, J. Bartel and D. Dussault, "Novel photolithography yield-enhancement technique: Megasonic - enhanced development", ECS Trans.¸ 33 (8), pp. 175, 2010.
 D. Figura and J. Bartel, "Fabrication of High Aspect Ratio SU-8 Structures Using UV Lithography and Megasonic-Enhanced Development" ECS Transactions, 25 (31) 29-35 (2010)
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Fig. 1: EVG® Developer Module with MegPie
Fig. 2: SU-8 structures: height 470µm, sidewall thickness 20µm, aspect ratio 1:23, development time 10min