3D-ICs with through silicon vias (TSVs) provide a large number of technical benefits in terms of the electrical performance, e.g., higher I/O bandwidth, shorter interconnect length, lower power consumption and better signal-to-noise ratio. The shorter interconnect length allows focus on one device function per layer, e.g., memory on one layer and logic on another layer. In the past, high-performance devices had to be designed and manufactured with the system-on-chip (SoC) approach. A SoC provides very good performance, but this comes at the cost of a very high design complexity. Chip stacking with TSVs enables devices with the highest performance within the system-in-package (SiP) family. Compared to SoCs, which require "re-inventing the wheel" with each device, with SiPs it is possible to follow a true modular design approach. Each company can focus on its device core competence, e.g., an ASIC or MEMS, and add standardized components like memory or logic controller from other suppliers.
Vertical interconnects enable a smaller form factor not only laterally, but also vertically. Stacking of dies allows working with smaller dies, which increases the wafer yield. Even more important is that stacking of dies enables heterogeneous integration. Silicon dies can be bonded to dies made of gallium arsenide (GaAs) or indium phosphide (InP).
There are many different integration and manufacturing schemes for 3D interconnects. One way to categorize the different integration schemes is by the orientation of the individual dies to each other. Figure 1 shows face-to-back (F2B) and face-to-face (F2F) integration. F2F integration does not require TSVs, whereas TSVs are required for F2B integration. For 2-layer chip stacks, both integration schemes have some advantages and disadvantages (Table 1). For multi-layer stacks, F2B has the advantage that after each bonding step the top device layer is face up so that the stacking unit process can be repeated multiple times. However, for F2B integration, the die/wafer has to have the final thickness already during stacking, as subsequent thinning is not possible.
Another, more popular, way to categorize 3D integration schemes is based on the point at which the TSV is created during the manufacturing process. In the past, the only distinction was whether the via was manufactured before or after wafer thinning: via-first or via-last. Today, it is common to further distinguish whether the via was created prior to front-end processing, i.e., via first, or after front-end processing (but before wafer thinning), i.e., via-middle. Figure 2 shows a typical process flow for via-middle manufacturing.
Another important distinction within the various integration schemes is based on wafer or die level processing: chip-to-chip (C2C), chip-to-wafer (C2W) and wafer-to-wafer (W2W). C2C has mainly been used for high performance, high margin devices. For lower margin devices like consumer electronics, C2C is not very suitable due to single die processing. Of course, W2W integration allows wafer-level processing after stacking. W2W integration gives the highest throughput and the highest alignment accuracy. But W2W integration requires that the dies have the exact same size, and it has the inherent risk that a defective die is bonded to a good die, thereby destroying the whole stack. C2W is a hybrid process and combines the single die placement with the feasibility of wafer-level processing after die placement.
With C2W integration, it is possible to stack dies of different sizes. With a modular design and chip architecture, it must be assumed that dies typically will have different sizes. For heterogeneous integration in particular, C2W is the method of choice as currently only silicon devices are manufactured on 300mm wafers, while all other semiconductor materials are being manufactured on smaller wafer sizes. In addition C2W enables testing of every die prior to stacking, which allows true "known good die" manufacturing. Figure 3 shows the difference between C2W and W2W integration.
Fortunately, all of the described manufacturing schemes are based on only a handful of key technologies. Temporary bonding of the device wafer to a carrier wafer enables thin wafer processing, which is independent of the specific process flow.
Figure 1: 3D integrations scheme categorized by the orientation of the dies to each other; face-to-back (F2B) stacking: after stacking the top device layer is face up; face-to-face (F2F) stacking: after stacking both device layers are facing each other within the bond interface. Courtesy of Yole Développment.
Table 1: Key characteristics of F2B and F2F integration
Figure 2: Via-middle process flow; The TSVs are created after frontend processing. The process flow is very similar to via-first. However, as the transistors have been already created, it is possible to use Cu or W vias.
Figure 3: Wafer-to-wafer (W2W) and chip-to-wafer (C2W) integration are most suitable for high volume manufacturing.