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EVG500 Series Short Brochure.pdf
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Vertical Integration through Aligned Permanent Bonding Techniques
Through-silicon-via (TSV) interconnects can provide the shortest length and the highest density with significantly reduced signal delay and power consumption. Due mainly to a thermal budget of CMOS devices, bonding processes compatible with CMOS processing are limited only to solder-based bonding, plasma-assisted oxide bonding, direct Cu-Cu bonding, polymer adhesive bonding, and metal-polymer hybrid bonding.
Effects of Bonding Process Parameters on the Interfacial Properties of Cu-Cu Direct Bonds for TSV Integration
Cu-Cu direct bonding facilitates fine-pitch interconnection with low electrical resistivity and high EM resistance. However, reliable Cu-Cu bonding stems only from high temperature, high pressure and long process time mainly because of its tendency to generate a native oxide which deadly impacts device reliability.
3D process integration – wafer-to-wafer and chip-to-wafer bonding Abstract:
Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes...
Advanced chip-to-wafer technology: Enabling technology for volume production of 3D system integration on wafer level
A continuous demand for electronic devices with more advanced functionality, in addition to decreased size and weight calls for ever-increasing integration and complexity. 3D system integration using chip-to-wafer technology offers the highest integration and performance of chip technology in combination with the flexibility and time-to-market advantages of packaging technology...