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EVG GEMINI®FB XT Product Flyer
EV Group GEMINI® 200mm Brochure.pdf
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Wafer Bonding for Backside Illuminated Image Sensors
Abstract: Backside illuminated image sensors combine small pixel area with high
signal-to-noise ratio. Wafer bonding is a key enabling process step for manufacturing of backside illuminated image sensors. The fully CMOS processed image sensor wafer is bonded to a blank silicon carrier wafer and then back thinned to reveal the photodiodes...
Wafer Bonding for Backside Illuminated CMOS Image Sensors Fabrication
Abstract: Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area...
Wafer Level Processing and Integration Techniques for CMOS Image Sensor Module Manufacturing
Abstract: Image sensors have become ubiquitous, appearing in cellular phones, car sensors, notebook webcams, digital cameras, video camcorders, and security & surveillance systems. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications...
Results on Aligned SiO2 /SiO2 Direct Wafer-to-Wafer Low Temperature Bonding for 3D Integration
Abstract: To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxideoxide direct bonding on 200mm with and without copper
level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.
Aligned fusion wafer bonding for wafer-level packaging and 3D integration
Abstract: Wafer-level packaging via wafer bonding allows smaller and thinner packages, improves the yield due to higher cleanliness, enables the encapsulation of vacuum or process gas and finally reduces the packaging costs significantly. High precision alignment of device wafer to cap wafer allows real chip size packaging as the required width of the sealing rings is in the low micron range...
Vertical Integration through Aligned Permanent Bonding Techniques
Abstract: Through-silicon-via (TSV) interconnects can provide the shortest length and the highest density with significantly reduced signal delay and power consumption. Due mainly to a thermal budget of CMOS devices, bonding processes compatible with CMOS processing are limited only to solder-based bonding, plasma-assisted oxide bonding, direct Cu-Cu bonding, polymer adhesive bonding, and metal-polymer hybrid bonding.
Trends in aligned wafer bonding for MEMS and IC wafer-level packaging and 3D interconnect technologies
Abstract: The continuous reduction of IC feature size, the increased demand for higher speed, the lower power consumption and the simultaneous increase of I/O leads to wafer-level packaging through aligned wafer bonding as an interesting solution for IC and MEMS packaging. Portable consumer products such as wireless handsets and upcoming high-performance computing devices drive the semiconductor industry to develop advanced packaging solutions with reduced thickness and area dimensions...
Effects of Bonding Process Parameters on the Interfacial Properties of Cu-Cu Direct Bonds for TSV Integration
Abstract: Cu-Cu direct bonding facilitates fine-pitch interconnection with low electrical resistivity and high EM resistance. However, reliable Cu-Cu bonding stems only from high temperature, high pressure and long process time mainly because of its tendency to generate a native oxide which deadly impacts device reliability.