GEMINI® Automated Production Wafer Bonding System

For fully automated and integrated wafer loading, alignment, bonding and unloading of bonded wafers.

 

Brochures

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EV Group GEMINI 200mm Brochure.pdf


EV Group GEMINI 300mm Brochure.pdf

Technical Papers
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Vertical Integration through Aligned Permanent Bonding Techniques
Abstract: Through-silicon-via (TSV) interconnects can provide the shortest length and the highest density with significantly reduced signal delay and power consumption. Due mainly to a thermal budget of CMOS devices, bonding processes compatible with CMOS processing are limited only to solder-based bonding, plasma-assisted oxide bonding, direct Cu-Cu bonding, polymer adhesive bonding, and metal-polymer hybrid bonding.



Effects of Bonding Process Parameters on the Interfacial Properties of Cu-Cu Direct Bonds for TSV Integration
Abstract: Cu-Cu direct bonding facilitates fine-pitch interconnection with low electrical resistivity and high EM resistance. However, reliable Cu-Cu bonding stems only from high temperature, high pressure and long process time mainly because of its tendency to generate a native oxide which deadly impacts device reliability.



3D interconnect through aligned wafer level bonding
Abstract: Wafer Level Packaging and 3-D Interconnect Technologies are driven by the increasing device density, functionality as well as the reduction of total packaging costs. Many devices such as PDAs, memory cards, smart cards and cellular phones utilize the resulting chip scale packages. Key enabling technologies for 3D Interconnect are high precision alignment and bonding systems and thick resist processing...



Aligned fusion wafer bonding for wafer-level packaging and 3D integration
Abstract: Wafer-level packaging via wafer bonding allows smaller and thinner packages, improves the yield due to higher cleanliness, enables the encapsulation of vacuum or process gas and finally reduces the packaging costs significantly. High precision alignment of device wafer to cap wafer allows real chip size packaging as the required width of the sealing rings is in the low micron range...



Advanced anodic bonding processes for MEMS applications
Abstract: Anodic bonding is a powerful technique used in MEMS manufacturing. This process is applied mainly for building three-dimensional structures for microfluidic applications or for wafer level packaging. Process conditions will be evaluated in present paper. An experimental solution for bonding three wafers in one single process step (“triple-stack bonding”) will be introduced...



Effects of bonding process parameters on wafer-to-wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding
Abstract: Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential...



New Challenges for 300 mm Si Technology - 3D Interconnects at Wafer Scale by Aligned Wafer Bonding

Abstract: A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 µm...



Trends in aligned wafer bonding for MEMS and IC wafer-level packaging and 3D interconnect technologies
Abstract: The continuous reduction of IC feature size, the increased demand for higher speed, the lower power consumption and the simultaneous increase of I/O leads to wafer-level packaging through aligned wafer bonding as an interesting solution for IC and MEMS packaging. Portable consumer products such as wireless handsets and upcoming high-performance computing devices drive the semiconductor industry to develop advanced packaging solutions with reduced thickness and area dimensions...



Wafer-scale BCB resist-processing technologies for high density integration and electronic packaging
Abstract: IC performance is drastically limited by line-to-line capacity coupling and RC interconnect delay times resulted from the continuous increase in integration densities with 0.10µm line and space width approaches, as well from increased signal frequencies. The new achievements in terms of circuit lines shrinkage emphasize the need for the introduction of Cu and low-k dielectric materials...