Application Focus – NanoSpray™
A key component for 2.5D/3D device integration schemes is the incorporation of vertical interconnections such as TSVs, which enable electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias.
Despite the potential benefits associated with the incorporation of TSVs, significant challenges must be overcome. One of the greatest challenges is the reduction of electrical losses (caused by insertion loss and crosstalk) and thermal-induced stress in the vicinity of metalized vias (caused by CTE mismatch). EVG has developed sophisticated advanced resist processing technologies that enable improved TSV interconnect designs and alleviate these issues.
By applying conformal sidewall linings of thick polymers (up to >5 µm thick) along the metal-substrate interface of TSVs, both insertion losses as well as electrical crosstalk are minimized over a large frequency band. In contrast to oxides and other inorganic liner materials, the cost of the application of polymers as barrier material also does not scale with the thickness of the deposited barrier material; and therefore reduces the cost of the process step. As a result, our NanoSpray™ technology empowers our customers with the freedom to design the optimum barrier layer according to their individual requirements.
In addition to having a crucial impact on shielding electrical losses, a thick polymer liner also greatly exceeds the abilities of thin oxide layers when it comes to improving thermo-mechanical performance of the metalized through-via. Due to its intrinsic elasticity, the polymer liner acts as a very effective stress buffer coating with the potential to eliminate thermal-induced stress in TSVs.
The short cycle times for the NanoSpray™ coating step further reduce cost of ownership (CoO) and enable processing of photoresist and other functional polymers at and within TSV geometries in order to bring 2.5D/3D packages one step closer to HVM environments.
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