EVGNEWS Issue 2 2013

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CoatsCleanTechnology Application Focus

The CoatsClean™ platform is a combination of both process and chemical technology featuring significantly reduced chemical usage, point-of-use heating, short process times, wafer-to-wafer consistency, and process flexibility in a single bowl tool. These advantages open up extensive opportunities in numerous fields of application, such as:

  • Post-etch residue removal (PERR) after DRIE (deep reactive ion etching) for creation of cavities, trenches, and vias for MEMS manufacturing as well as deep TSV creation in general.
  • Fast and effective stripping of various hard-to-remove photoresists for packaging applications 


CoatsClean formulation is engineered to balance cleaning performance with material compatibility at higher temperatures.

Photoresist Stripping for Advanced Packaging Applications

CoatsClean technology targets the emerging needs of wafer-level packaging, including the removal of: thick, highly cross-linked films such as photoresists and fluxes while the blunt does not attack different different solder bump types, including eutectic, lead-free, and copper pillar; exposed metals; under-bump metallization; and dielectric layers. 

The results presented at right show the capability to remove both thick liquid and dry film photoresist on wafers with different solder bump types - including eutectic, lead-free, and copper pillar - for the production of advanced packaging applications.

The formulation is heated on the wafer to the desired temperature, and then held at that temperature for a specified time. Once the photoresist is dissolved, the wafer is rinsed to remove the formulation, dissolved photoresist, and residue. Finally, the wafer is dried by spin drying.

CoatsClean provides a new approach to photoresist removal and wafer cleaning. It uses custom-designed chemistry combined with an optimal process on the flexible EVG300RS tool series - which features a small footprint, environmental sustainability, and reduced EH&S concerns - to provide a lower cost of ownership compared to traditional resist strip processes.

The multidisciplinary approach effectively integrates the chemistry for resist removal, the wafer cleaning process and the tool platform simultaneously, to deliver a flexible single-bowl cleaning process. Cleaning and etch results from bumped 200 mm and 300 mm wafers with up to 120µm thick negative dry film using a new single-wafer clean tool and process are demonstrated at right.

CoatsClean™ Technology for Compound Semiconductor Manufacturing

The CoatsClean platform is ideally suited to remove post-etch residue in the production of GaAs heterojunction bipolar transistors (HBTs) for both polyimide via and base pedestal layers.
The CoatsClean technology not only provides flexibility in photoresist cleaning processes, but also provides the ability to balance resist removal with materials compatibility, increased stability of chemical formulations, and the ability to run multiple wafer types and chemistries on the same tool.

Many compound semiconductor (CS) devices rely on vias for low inductance grounding and increased circuit complexity. Post-etch residue removal is also a challenging task. CoatsClean provides an innovative single-wafer stripping process to address these issues.

Polyimide Via Resist Strip

Polyimides are commonly used for electrical isolation in CS devices. Besides pure electrical isolation, polyimides offer low permittivity for improved high-frequency behavior as well as encapsulation of the active transistors from ambient active transistors.
Electrical connection is achieved by via etching, forming so-called polyimide vias. Most crucial for this process is the precise removal of photoresist masks after etching, without damaging the polyimide layer.

Via openings are patterned in a positive photoresist and then etched through the polyimide using an O2 plasma. The remaining photoresist is stripped from the underlying polyimide by CoatsClean formulation.

Base Pedestal Resist Strip

Accurate etch definition of Base Pedestal (BP mesa) is key for proper device performance. For this reason, a combination of dry and wet etching is applied, delivering accurate edge definition and reducing plasma induced defects. However this introduces major challenges for the subsequent resist stripping step.

The same CoatsClean formulation that is used for polyimide via strip can also be applied to strip the post-etch residue from the BP mesa.

 

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Click to download our joint paper "A New Single Wafer Cleaning Technology for Compound Semiconductor Manufacturing"

fig2_thumb   Fig. 1: Optical micrographs and SEM images illustrating complete resist removal.

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Fig. 2: Optical micrographs illustrating complete Cu field metal etch  

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Fig. 3: SEM images of the polyimide via (PV) strip process

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Fig. 4: NSX-100 wafer map for the PV strip process with CoatsClean™ showing 99.3% die yield.  

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Fig. 5: SEM images of the BP strip process: [left] unstripped and [right] after CoatsClean™  strip.